New Silicon Insider Article

Article: Sizing up the Super Heavyweights
By: Paul DeMone (pdemone.delete@this.igs.net), October 22, 2004 10:38 am
Room: Moderated Discussions
Arun Ramakrishnan (arunr@sgi.com) on 10/22/04 wrote:
---------------------------
[..]
>Why would the L2 I-cache be about 4 times the size of the L2 D-cache ?
>I always thought that MPU desginers would try to cut the latency of access to user
>data much more than the intruction stream itself.

IA-64 has low code density. A 1.0 MB/256KB IPF design
has similar instruction/data balance as roughly a 512
KB/256 KB RISC design. A bigger L2 icache also reduces
average instruction stream bandwidth demand on the L3.

>
>Would this have something to do with the fact that two coarse grained threads on
>the core need to fed rapidly in order to keep the CMP efficiency high ?

Yep, that's probably the biggest reason. I also suspect
it will give a noticable boost to IA-32 EL performance.
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New Silicon Insider ArticleDavid Kanter2004/10/11 05:43 AM
  Good read. Thanks again Paul. (NT)Michael Menietti2004/10/11 06:36 AM
  New Silicon Insider ArticleSingh, S.R.2004/10/11 06:44 AM
    New Silicon Insider ArticlePaul DeMone2004/10/11 06:55 AM
  New Silicon Insider Articletecate2004/10/11 09:52 AM
  core size: x86 vs IPFanonymous2004/10/11 11:43 AM
    Good Question. (NT)Chuck2004/10/12 08:22 AM
    core size: x86 vs IPFMichael S2004/10/12 10:53 AM
    K8 core size 52mm^2IlleglWpns2004/10/12 12:15 PM
    core size: x86 vs IPFPaul DeMone2004/10/12 01:10 PM
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    New Silicon Insider ArticlePaul DeMone2004/10/17 06:58 AM
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    New Silicon Insider ArticlePaul DeMone2004/10/22 10:38 AM
      New Silicon Insider ArticleDavid Kanter2004/10/22 11:04 PM
        New Silicon Insider ArticlePaul DeMone2004/10/23 06:02 AM
        New Silicon Insider ArticleArun Ramakrishnan2004/10/23 01:47 PM
      New Silicon Insider ArticleMichael S2004/10/23 11:38 AM
        New Silicon Insider ArticlePaul DeMone2004/10/23 01:10 PM
          New Silicon Insider ArticleMichael S2004/10/23 01:40 PM
  Do I see a flaw here?IntelUser20002004/10/27 05:43 PM
    Frequency is different for startersPaul DeMone2004/10/27 06:05 PM
      Frequency is different for startersIntelUser2004/10/27 06:28 PM
        Frequency is different for startersPaul DeMone2004/10/27 07:49 PM
          Frequency is different for startersIntelUser20002004/10/27 08:45 PM
  New Silicon Insider ArticleIntelUser20002004/11/01 10:13 AM
    New Silicon Insider Articleanonymous2004/11/02 09:46 AM
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      New Silicon Insider ArticleDavid Kanter2004/11/05 08:44 AM
        New Silicon Insider ArticleIntelUser20002004/11/08 08:23 PM
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