Article: CELL Microprocessor Revisited
By: David Wang (dwang.delete@this.RWTexpanded.com), March 7, 2005 4:45 pm
Room: Moderated Discussions
Ricardo Bugalho (ricardo.b@zmail.pt) on 3/7/05 wrote:
---------------------------
>Page 2
>Figure 1 above illustrates an XDR memory system with a 16 bit wide data bus
>(For the purpose of illustration only. The XDR memory system on the CELL processor
>has two physical channels that are 36 bits wide per channel).
>
>Isn't 36 a typo?
No, it's 36. The CELL processor supports ECC (optionally).
---------------------------
>Page 2
>Figure 1 above illustrates an XDR memory system with a 16 bit wide data bus
>(For the purpose of illustration only. The XDR memory system on the CELL processor
>has two physical channels that are 36 bits wide per channel).
>
>Isn't 36 a typo?
No, it's 36. The CELL processor supports ECC (optionally).
| Topic | Posted By | Date |
|---|---|---|
| CELL Microprocessor Revisited | David Kanter | 2005/03/07 11:21 AM |
| CELL Microprocessor Revisited | Ricardo Bugalho | 2005/03/07 03:05 PM |
| CELL Microprocessor Revisited | David Wang | 2005/03/07 04:45 PM |
| CELL Microprocessor Revisited | hobold | 2005/03/08 08:10 AM |
| CELL Microprocessor Revisited | mas | 2005/03/27 08:27 PM |
