mas () on 8/2/05 wrote:
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> So with 7 SPEs we can say for every cycle the SPEs provide
>2 DP FMADD and the PPE 1 DP FMADD giving 6 DP flops/cycle. 3.2 Ghz gives 19.2 peak
>DP GFlops which means for reference that I2/P5 could match this peak at 4.8 Ghz
>although how much a Cell could sustain in practice is not certain.

It'll be harder to maintain peak DP FP, especially since you have to use separate tool chains for the SPE and the PPE. So you have to do a clean-sheet re-think about how to utilize the asymmetric threading model and keep the functional units busy. I think that you'll probably have to make your choice to run with "legacy" PPC ISA and get the FP performance there, or go with the SPE only.

OTOH, if you looked at the photo micrographs of the SPE and the PPE closely, you'll see that the PPE itself isn't that much larger than the SPE, and if there's a market for this sort of thing, IBM could spin a DD3 where the 7 cycle penalty for DP FMADD goes away. Such a chip could crank out enormous amounts of (peak) DP FP, but the flop to BW ratio would be heavily skewed to the flop side of things, even if IBM goes with 8 Gb/s/pin-pair XDR2.

> Coincidentally
>by having 3 PPEs the Xenon in Xbox 360 could match that DP figure with its SP rate
>being 76.8 Gflops vs Cell's 204.8 so it doesn't look so outclassed as one would
>think given Cell's hype. I have also heard development Cell kits are only at 2.4
>Ghz. Anyway they both sound like great distributed computing clients I hope Sony
>and Microsoft allow them to be used in that ancillary fashion.

If they're going to heavily subsidize the consoles, they may not like the idea of people buying them for compute farms.