New CELL Article Online

Article: CELL Microprocessor III
By: David Wang (dwang.delete@this.RWTexpanded.com), August 2, 2005 6:27 pm
Room: Moderated Discussions
fastpathguru (fastpathguru@yahoo.com) on 8/2/05 wrote:
---------------------------

>Re: The Mystery of the Missing FLOPS, is it possible that it's solved by accounting
>for the extra meat in the PPE? I didn't see that mentioned as a possibility.

You need 68 flops per cycle to get 218 GFlops @ 3.2 GHz.

It's easy to get 56 of those flops from 7 SPE's, using FMADD, but then you'd need 12 flops per cycle out of the PPE to get to 68.

Again, assume that you can crank 8 Flops per cycle out with FMADD, you still need 4 flops per cycle. The PPE is multi-threaded, but the impression that I got from the IBM folks is that the scalar and vector FP units are actually shared so you really can't get more flops out of the PPE either. Regardless, even if the FP units aren't shared, you still can't get 4 flops per cycle out of the scalar side of thing.

So no, the beefier PPE can't get to 12 flops per cycle even if it had independent scalar/vector FP units.
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