New CELL Article Online

Article: CELL Microprocessor III
By: David Wang (, August 3, 2005 11:28 am
Room: Moderated Discussions
Panajev2001a ( on 8/3/05 wrote:
>David Wang ( on 8/2/05 wrote:
>>fastpathguru ( on 8/2/05 wrote:
>>>Re: The Mystery of the Missing FLOPS, is it possible that it's solved by accounting
>>>for the extra meat in the PPE? I didn't see that mentioned as a possibility.
>>You need 68 flops per cycle to get 218 GFlops @ 3.2 GHz.
>>It's easy to get 56 of those flops from 7 SPE's, using FMADD, but then you'd need
>>12 flops per cycle out of the PPE to get to 68.
>>Again, assume that you can crank 8 Flops per cycle out with FMADD, you still need
>>4 flops per cycle. The PPE is multi-threaded, but the impression that I got from
>>the IBM folks is that the scalar and vector FP units are actually shared so you
>>really can't get more flops out of the PPE either. Regardless, even if the FP units
>>aren't shared, you still can't get 4 flops per cycle out of the scalar side of thing.
>>So no, the beefier PPE can't get to 12 flops per cycle even if it had independent scalar/vector FP units.
>Why not ? See Gekko ;).

I've forgotten about Gekko entirely.

So the 12 Flops/cycle can be attained by the PPE if the PPE's scalar FPU can do a 2 wide SP FMADD in addition to a separate and independent Altivec unit. That does make things quite curious. I'm not sure how many programmers will be able to make use of this capability, but I think you're right, the Gekko ISA extension to the DD2 PPE explanation sounds to be the most reasonable explanation that I have come across about how Sony was able to claim the 218 GFlops rating with only 7 SPE's @ 3.2 GHz.

Perhaps you can write a rebuttal article and we can link it to the current article. I think the readership in general will benefit from this discussion.

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