New CELL Article Online

Article: CELL Microprocessor III
By: David Wang (, August 4, 2005 5:47 pm
Room: Moderated Discussions
Deadmeat ( on 8/4/05 wrote:
>I appreciate your article. A few things to add.
>1. DD2 PPE is what SCEI intended all along for PSX3. DD1 PPE might be used for lower cost CELL variants.
>2. Why PSX3 CELL needs a more powerful core has everything to do with its programming
>model. CELL employees an "offshoring" processing model. To utilize CELL's APU, you
>first start with 7 CPU threads, each of which then gains a synchronous access to
>one of 7 APUs available. Each CPU thread then loads the APU with required data and
>code, kick(initiate) it, then goes into wait status until APU is done and interrupts
>the CPU thread, which then reads back the processed data from APU(Which looks like
>a memory file to the coder). But to efficiently utilize the APU at all time, you
>may need twice as many CPU threads active, which means at least 14 active threads
>or more. You need a fairly powerful CPU handle all those threads.

Why do you need to schedule all the threads independently? Are you writing independent modules/streams that consist of 1 thread each and then trying to keep all the threads up in the air dynamically? I think if that's how you're writing the threads, perhaps you shouldn't be surprised the processor will start to drop (real time) threads on you.

If I may quote from Maeda-san's presentation, he states

"Scheduling overhead is ... < 1 MS ... when 16 threads are running and requested to accest 4 new threads with precedence constraints"


"Scheduling is required only when new stream starts processing"

I looked at those slides a few times and read them as "scheduling? no problem. low overhead."

Whether that's true or overly optimistic is another story, but that's how I read them.

So even if you're trying to crunch video at 30 frames per second, I'd think that the scheduling overhead should be relatively low and could be handled by a very simplistic core.

>3. Your DD1/DD2/970 core comparison pic is out of scale. 970 core is twice as large
>as DD2 PPE core(26 mm2 according to my measurement) and weights 18 million transistors.

I went back and looked at the picture, apparently it is a bit off. My measurements show a height of ~5.9 mm for DD2 PPE and the height of ~6.9 mm for PPC970FX core from the top of the vector units to the bottom of the L1 I$. The current picture shows PPC970FX core to be ~6.5 mm tall rather than 6.9 mm. Roughly, The PPC970FX core should've been about 17% taller rather than merely 10% taller.

Here's the current picture

Here's a corrected picture.

>4. MS is evidently not using the PPE DD2, in contrary to the popular belief. Their
>transistor budget for the core(33 million each) is too high to be a PPE DD2(18 million).

I didn't get into the Xenon vs CELL discussion, but
do you have a reference for these numbers? Panajev2001 pointed me to a photograph of a supposed Microsoft presentation. The presented slide claims 12 flops per cycle, and that matches the 8 Altivec flops + 4 Gekko flops number that we're assuming for DD2 PPE here. Moreover, a difference of 15 million transistors per core is far too drastic to be accounted for in terms of logic transistors, so something doesn't seem quite right there. Either the cache architecture is different or something is being misquoted.
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                              Implausible at best, irrational most likely...David Kanter2005/08/08 06:51 PM
                                Implausible at best, irrational most likely...Deadmeat2005/08/09 10:26 AM
                              New CELL Article OnlineDavid Wang2005/08/08 07:46 PM
                                New CELL Article OnlineDeadmeat2005/08/09 10:36 AM
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