> Why do you need to schedule all the threads independently?

Because only one CPU thread can access one APU at a time(the moment the CPU thread kicks the APU, it is immediately preempted from the running queue and put to sleep/wait until the APU execution is over), so you need to have 7 CPU threads that have issued a job to an APU each to utilize all seven at any given moment.

> Are you writing independent modules/streams that consist of 1 thread each and then trying to keep all the threads up in the air dynamically?

That's how CELL was designed.

> I think if that's how you're writing the threads, perhaps you shouldn't be surprised the processor will start to drop (real time) threads on you.

While the APU runs, the kicking CPU thread is on sleep until the kicked APU finishes. So there is no dropping of thread issue.

The philosophical difference between CELL and Xbox CPU is offshoring Vs inhouse. In case of CELL, there are two American managers, who prepare specifications to be processed by 7 Indians. But before the specification is shipped to India, they must first prepare it in Hindi(our Indian coders are cheap and don't speak English), ship it by boat(DMA transfer takes time, wait until it is finished, then have it mailed back.

In case of Xbox processor, nothing is offshored, everything is done inhouse by six experienced coders sitting in the same room, at the cost of much higher rent and salary.

So which produces more work/dollar, 7 Indians coding away in India + Time to ship it back and forth, or 6 highlys-skilled American programmers making $100/hr?

> So even if you're trying to crunch video at 30 frames per second, I'd think that the scheduling overhead should be relatively low and could be handled by a very simplistic core.

That's is what CELL is good for, video/audio processing only. This thing is clearly unsuitable for physics processing and AI.

> I didn't get into the Xenon vs CELL discussion, but do you have a reference for these numbers?

I calculated that figure by first calculating the logic transistor density of APU(sans SRAM Local Memory), then using this density to estimate the transistor count of PPE itself. It is only an estimate, but should be fairly good.

> Roughly, The PPC970FX core should've been about 17% taller rather than merely 10% taller.

Just compare two, and it is quite obvious that 970 core is twice as large as DD2 PPE in terms of area.

> Moreover, a difference of 15 million transistors per core is far too drastic to be accounted for in terms of logic transistors, so something doesn't seem quite right there. Either the cache architecture is different or something is being misquoted.

No misquote, 165 million transistors for 3 cores + 1 MB cache + hypertransport bus controller.