New CELL Article Online

Article: CELL Microprocessor III
By: David Wang (, August 4, 2005 9:03 pm
Room: Moderated Discussions
Deadmeat ( on 8/4/05 wrote:
>> Why do you need to schedule all the threads independently?
>Because only one CPU thread can access one APU at a time(the moment the CPU thread
>kicks the APU, it is immediately preempted from the running queue and put to sleep/wait
>until the APU execution is over), so you need to have 7 CPU threads that have issued
>a job to an APU each to utilize all seven at any given moment.

>> Are you writing independent modules/streams that consist of 1 thread each and
>then trying to keep all the threads up in the air dynamically?
>That's how CELL was designed.

You can always give up some efficiency in terms of 100% utilizaton of the SPE's by declaring explicitly parallel threads that are group scheduled. The grouping of threads within the modules means that only the modules have to be scheduled with respect to each other. The group scheduling assuming is what Maeda-san presented as having less than 1 ms overhead per scheduling event. Certainly you can't always get away with a bunch of modules that all have 7+ threads within each, but it seems to me that you don't always need complete thread independence either.

>> I think if that's how you're writing the threads, perhaps you shouldn't be surprised
>the processor will start to drop (real time) threads on you.
>While the APU runs, the kicking CPU thread is on sleep until the kicked APU finishes.
>So there is no dropping of thread issue.

That's from the real time scheduler presentation. Modules won't be accepted for scheduling unless the specified real time constraints can be met.

>> I didn't get into the Xenon vs CELL discussion, but do you have a reference for these numbers?
>I calculated that figure by first calculating the logic transistor density of APU(sans
>SRAM Local Memory), then using this density to estimate the transistor count of
>PPE itself. It is only an estimate, but should be fairly good.

This is too wild of an estimate I think. How many transistors did you assume to be contained in the L1 I$ and d$ data arrays and tags?

>> Roughly, The PPC970FX core should've been about 17% taller rather than merely 10% taller.
>Just compare two, and it is quite obvious that 970 core is twice as large as DD2 PPE in terms of area.

I don't see 2X larger. I looks to be less than 50% larger. That is, when the bus interface, the L2 cache, the PLL and that sort of thing are excluded from both.

>> Moreover, a difference of 15 million transistors per core is far too drastic
>to be accounted for in terms of logic transistors, so something doesn't seem quite
>right there. Either the cache architecture is different or something is being misquoted.
>No misquote, 165 million transistors for 3 cores + 1 MB cache + hypertransport bus controller.

What associativity/port count are you using for the 1 MB L2, and how many transistors are you subtracting from the 165M number for the L2?
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                              Implausible at best, irrational most likely...David Kanter2005/08/08 06:51 PM
                                Implausible at best, irrational most likely...Deadmeat2005/08/09 10:26 AM
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