New CELL Article Online

Article: CELL Microprocessor III
By: Deadmeat (deadmeatoa.delete@this.yahoo.com), August 5, 2005 12:21 pm
Room: Moderated Discussions
> You can always give up some efficiency in terms of 100% utilizaton of
> the SPE's by declaring explicitly parallel threads that are group scheduled.

Only one CPU thread can access and kick an APU at a time. To have it group scheduled,
you start with one CPU thread that spawns 6 other CPU threads, which gain an access to
one APU each, and kick them all at once.

7 CPU threads are needed to kick 7 APUs, why is this so hard to understand?

> Certainly you can't always get away with a bunch of modules that all have 7+
> threads within each, but it seems to me that you don't always need complete
> thread independence either.

Somebody does have to spawn threads, be it the application coder or the middle
engine coder.

> This is too wild of an estimate I think.

Do you have a better way of estimation? This is a brand new architecture with no known
relatives, other than the APUs which shares some of execution units.


> I don't see 2X larger. I looks to be less than 50% larger.

1.4X in length * 1.4X in length = 2X as large in area.

> What associativity/port count are you using for the 1 MB L2, and how many transistors
> are you subtracting from the 165M number for the L2?

58 million transistors from 1 MB L2 cache and 8 million transistors from HyperTransport
and other logics.
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                              Implausible at best, irrational most likely...David Kanter2005/08/08 06:51 PM
                                Implausible at best, irrational most likely...Deadmeat2005/08/09 10:26 AM
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