New CELL Article Online

Article: CELL Microprocessor III
By: David Wang (, August 5, 2005 11:51 pm
Room: Moderated Discussions
Deadmeat ( on 8/5/05 wrote:
>> You can always give up some efficiency in terms of 100% utilizaton of
>> the SPE's by declaring explicitly parallel threads that are group scheduled.
>Only one CPU thread can access and kick an APU at a time. To have it group scheduled,
>you start with one CPU thread that spawns 6 other CPU threads, which gain an access to
>one APU each, and kick them all at once.
>7 CPU threads are needed to kick 7 APUs, why is this so hard to understand?
>> Certainly you can't always get away with a bunch of modules that all have 7+
>> threads within each, but it seems to me that you don't always need complete
>> thread independence either.
>Somebody does have to spawn threads, be it the application coder or the middle
>engine coder.

A couple of things.

You don't have to dynamically construct the SPE threads, then hand feed the text and data into the SPEs. I'm not sure which programming model you're following, but that is not the only programming model that is possible.

A couple more things on the topic.

IBM will be rolling out a series of tutorials and papers on the programming model and the toolchain. IBM is also apparently working on a unified toolchain that will handle the PPE and the SPEs concurrently.

Some interesting links

IBM's cell compiler project, with links to performance eval and publications.

Upcoming Tutorial on CELL Processor Architecture and Compilation Techniques (part of PACT 05)

And there's also a paper on the Optimizing compiler for the CELL processor in PACT 05.

>> I don't see 2X larger. I looks to be less than 50% larger.
>1.4X in length * 1.4X in length = 2X as large in area.

As I wrote in a previous post. The PPC970FX core from the top of the SIMD units to the bottom of the L1 I$ is 6.9 mm in height, and the DD2 PPE is 5.9 mm in height. The PPC970FX core (without the L2 cache, the bus interface, the PLL etc) is nowhere close to 2X larger than the DD2 PPE.

>> What associativity/port count are you using for the 1 MB L2, and how many transistors
>> are you subtracting from the 165M number for the L2?
>58 million transistors from 1 MB L2 cache and 8 million transistors from HyperTransport
>and other logics.

I think the 58M transistor count is too low for a 1 MB L2 that feeds 3 high speed SMT cores, and 8M is too large for "glue + misc stuff". I think if and when Xenon details are make public, there'll be a lot more transistors budget in the cache and a lot less in the cores.

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