>Unfortunately, it does not. You're presuming that the 68 FLOPS per cycle that Sony
>is claiming are all FADD or FMULTS, then seeking to justify where those FADD/FMULT
>must come from. There's no support for that presumption in this slide or any other slide I have seen.

Sure there is. The CPU core is clearly dual issue; it can issue only two instructions per cycle max. The FPU/Altivec unit instruction queue can issue two instructions per cycle max.

This means that 12 FLOPS must be provided within that two instructions. Altivec provides 8 FLOPS. FPU provides 4 FLOPS.

> The answer I received was in essence "no comment". **

Since MS is claiming the same 38.4 GFLOPS/s per core, it is not some number pulled out of a marketing manager's imagination.

>The best alternate theory not having anything to do with Gekko and still make the
>218 GFLOPS number is that Sony is counting some sort of load/store/comparison instruction
>as a 4 wide "FP" operation for the DD2 PPE.

SCEI didn't go that low with PSX2's VU FLOPS, and I am not about to believe that they would go even lower than PSX2's FLOPS counting methodology.

BTW, they don't even consider load/store into FLOPS rating, all theoretical FLOPS claims are obtained by assuming repeated FMAC instructions only.

>So we're back to square one.

I am convinced that Gecko FLOPS are at work here, especially looking at that diagram, so this issue is settled for me.