Article: CELL Microprocessor III
By: David Wang (dwang.delete@this.RWTexpanded.com), August 8, 2005 5:47 pm
Room: Moderated Discussions
Deadmeat (Deadmeatoa@yahoo.com) on 8/8/05 wrote:
---------------------------
>>Unfortunately, it does not. You're presuming that the 68 FLOPS per cycle that Sony
>>is claiming are all FADD or FMULTS, then seeking to justify where those FADD/FMULT
>>must come from. There's no support for that presumption in this slide or any other slide I have seen.
>
>Sure there is. The CPU core is clearly dual issue; it can issue only two instructions
>per cycle max. The FPU/Altivec unit instruction queue can issue two instructions per cycle max.
>
>This means that 12 FLOPS must be provided within that two instructions. Altivec provides 8 FLOPS. FPU provides 4 FLOPS.
I think there's some sort of circular reasoning going on here now. I'm questioning Sony's methodology for counting FLOPS (because I've ran out of other more reasonable explanations), but you're simply re-asserting the 12 FMAC FLOPS per cycle assumption for DD2 PPE... And round and round we go.
>> The answer I received was in essence "no comment". **
>
>Since MS is claiming the same 38.4 GFLOPS/s per core, it is not some number pulled
>out of a marketing manager's imagination.
That too adds to the puzzle.
>>The best alternate theory not having anything to do with Gekko and still make the
>>218 GFLOPS number is that Sony is counting some sort of load/store/comparison instruction
>>as a 4 wide "FP" operation for the DD2 PPE.
>
>SCEI didn't go that low with PSX2's VU FLOPS, and I am not about to believe that
>they would go even lower than PSX2's FLOPS counting methodology.
>
>BTW, they don't even consider load/store into FLOPS rating, all theoretical FLOPS
>claims are obtained by assuming repeated FMAC instructions only.
>
>>So we're back to square one.
>
>I am convinced that Gecko FLOPS are at work here, especially looking at that diagram, so this issue is settled for me.
Then we are at an impasse.
As I wrote previously, I would only be too happy to believe that the "Gekko FPU" is what accounts for the 4 additional FLOPS per cycle. It certainly makes things neat and tidy. All of the bits and pieces of ancillary evidence would just fit together nicely. As of 5 days ago, I already accepted the "Gekko FPU" theory as being the most likely and highly plausible explanation.
Unfortunately, I have two negative feedbacks on this theory from people whose credibility and veracity I could not impeach. I either have to believe that they're unaware of the Gekko addition to the DD2 PPE or that both of them are purposefully deceiving me. At this point in time, I have no evidence to either case being true or even likely. So in addition to all the available ancillary evidence, I have to reconcile the conflicting statements made by these "experts", one of whom made the very slide you cited as supporting evidence.
---------------------------
>>Unfortunately, it does not. You're presuming that the 68 FLOPS per cycle that Sony
>>is claiming are all FADD or FMULTS, then seeking to justify where those FADD/FMULT
>>must come from. There's no support for that presumption in this slide or any other slide I have seen.
>
>Sure there is. The CPU core is clearly dual issue; it can issue only two instructions
>per cycle max. The FPU/Altivec unit instruction queue can issue two instructions per cycle max.
>
>This means that 12 FLOPS must be provided within that two instructions. Altivec provides 8 FLOPS. FPU provides 4 FLOPS.
I think there's some sort of circular reasoning going on here now. I'm questioning Sony's methodology for counting FLOPS (because I've ran out of other more reasonable explanations), but you're simply re-asserting the 12 FMAC FLOPS per cycle assumption for DD2 PPE... And round and round we go.
>> The answer I received was in essence "no comment". **
>
>Since MS is claiming the same 38.4 GFLOPS/s per core, it is not some number pulled
>out of a marketing manager's imagination.
That too adds to the puzzle.
>>The best alternate theory not having anything to do with Gekko and still make the
>>218 GFLOPS number is that Sony is counting some sort of load/store/comparison instruction
>>as a 4 wide "FP" operation for the DD2 PPE.
>
>SCEI didn't go that low with PSX2's VU FLOPS, and I am not about to believe that
>they would go even lower than PSX2's FLOPS counting methodology.
>
>BTW, they don't even consider load/store into FLOPS rating, all theoretical FLOPS
>claims are obtained by assuming repeated FMAC instructions only.
>
>>So we're back to square one.
>
>I am convinced that Gecko FLOPS are at work here, especially looking at that diagram, so this issue is settled for me.
Then we are at an impasse.
As I wrote previously, I would only be too happy to believe that the "Gekko FPU" is what accounts for the 4 additional FLOPS per cycle. It certainly makes things neat and tidy. All of the bits and pieces of ancillary evidence would just fit together nicely. As of 5 days ago, I already accepted the "Gekko FPU" theory as being the most likely and highly plausible explanation.
Unfortunately, I have two negative feedbacks on this theory from people whose credibility and veracity I could not impeach. I either have to believe that they're unaware of the Gekko addition to the DD2 PPE or that both of them are purposefully deceiving me. At this point in time, I have no evidence to either case being true or even likely. So in addition to all the available ancillary evidence, I have to reconcile the conflicting statements made by these "experts", one of whom made the very slide you cited as supporting evidence.
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