Intel Tulsa Coverage from ISSCC

Article: ISSCC 2006: Intel Tulsa
By: David Kanter (, February 21, 2006 2:45 am
Room: Moderated Discussions
Fellow RWTers,

In continuing with our tradition* of having regular articles, here is one for Tuesday.


This article describes the architecture of Tulsa, and focuses on the techniques Intel used to address leakage, the rationale behind the shared L3 cache and how it suites Intel's system architecture and concludes with a schmoo plot and some comments about Intel's 65nm process.

Take a look and give us some feedback!


*OK, so this tradition basically started last week, and we're hoping to keep it up for a while, but who knows?
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TopicPosted ByDate
Intel Tulsa Coverage from ISSCCDavid Kanter2006/02/21 02:45 AM
  Intel Tulsa Coverage from ISSCCAlberto2006/02/21 04:43 AM
    Intel Tulsa Coverage from ISSCCPaul DeMone2006/02/21 06:52 AM
  Inclusive L3? WowMichael S2006/02/21 04:51 AM
    Inclusive L3? WowWouter Tinus2006/02/21 07:06 AM
      Inclusive L3? WowMichael S2006/02/21 08:20 AM
        Inclusive L3? Wowslim2006/02/21 11:40 AM
    It is?anonymous2006/02/21 09:57 AM
    Inclusive L3? WowLinus Torvalds2006/02/21 10:10 AM
      Inclusive L3? WowMichael S2006/02/21 11:03 AM
        Inclusive L3? WowLinus Torvalds2006/02/21 11:52 AM
          Inclusive L3? WowEric Bron2006/02/22 06:39 AM
            Inclusive L3David Kanter2006/02/22 12:16 PM
              Inclusive L3Eric Bron2006/02/22 01:00 PM
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