Inclusive L3? Wow

Article: ISSCC 2006: Intel Tulsa
By: Michael S (already5chosen.delete@this.yahoo.com), February 21, 2006 8:20 am
Room: Moderated Discussions
Wouter Tinus (wouter@tweakers.net) on 2/21/06 wrote:
---------------------------
>Michael S (already5chosen@yahoo.com) on 2/21/06 wrote:
>---------------------------
>>It should be rather complex to build inclusive cache that has to stay in synch
>>with not one, not two, but SIX inner caches!
>
>How do you get six? I just count 2x L1 and 2x L2.

+ 2x L1I caches


>And is it really that complex compared to other L3 caches?

I am not aware of other inclusive shared L3 caches implemented on ISA that requires hardware-enforced consistency between I and D caches.

>I thought Intel used write-through to keep levels of
>cache synchronized.

Only L1D. L2 is WB. But even with WT things remain rather complex.

>Intuitively keeping track of updates from two cores shouldn't
>be much harder than with just one core, you just need more bandwidth (but thats inherent to sharing cache).
>

I have very limited understanding of implementation techniques used for inclusive caches. It seems to me that the outer cache would have to keep track for the "inner" ownership for each cache line. So each and every inner-cache eviction shoudl be reported to the outer cache.

>What added complexity do you see, and do you think an exclusive cache would be simpler? Thanks.

I don't think that shared exclusive cache would be much simpler. Still all evictions from inner levels should be reported to the outer level. But at least outer level don't have to care about the source of the evicted line.
However classic Intel "independently managed" cache _is_ much simpler than either exclusive or inclusive variant.
Of course, David is 100% correct when he says that inclusive cache is wastly preferable from system perspective when you have a lot of sockets.

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Intel Tulsa Coverage from ISSCCDavid Kanter2006/02/21 02:45 AM
  Intel Tulsa Coverage from ISSCCAlberto2006/02/21 04:43 AM
    Intel Tulsa Coverage from ISSCCPaul DeMone2006/02/21 06:52 AM
  Inclusive L3? WowMichael S2006/02/21 04:51 AM
    Inclusive L3? WowWouter Tinus2006/02/21 07:06 AM
      Inclusive L3? WowMichael S2006/02/21 08:20 AM
        Inclusive L3? Wowslim2006/02/21 11:40 AM
    It is?anonymous2006/02/21 09:57 AM
    Inclusive L3? WowLinus Torvalds2006/02/21 10:10 AM
      Inclusive L3? WowMichael S2006/02/21 11:03 AM
        Inclusive L3? WowLinus Torvalds2006/02/21 11:52 AM
          Inclusive L3? WowEric Bron2006/02/22 06:39 AM
            Inclusive L3David Kanter2006/02/22 12:16 PM
              Inclusive L3Eric Bron2006/02/22 01:00 PM
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