Michael S (already5chosen@yahoo.com) on 2/21/06 wrote:
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>Wouter Tinus (wouter@tweakers.net) on 2/21/06 wrote:
>---------------------------
>>Michael S (already5chosen@yahoo.com) on 2/21/06 wrote:
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>>>It should be rather complex to build inclusive cache that has to stay in synch
>>>with not one, not two, but SIX inner caches!
>>

It would be complex if you tried to design it to be automatically inclusive of upper caches. Most commonly inclusion is acomplished via the issuanace of a back-invalidate (BI) to the upper caches whenever the L3 evicts a line. This is called forced inclusion and is independent of the number or architecture of the upper caches.

Eviction hints are "nice" but not required. Note that on Xeon the writeback of a cache line does not imply that a copy does not exist in another cache. (Implicit WB excepted).

>>How do you get six? I just count 2x L1 and 2x L2.
>
>+ 2x L1I caches
>
>
>>And is it really that complex compared to other L3 caches?
>
>I am not aware of other inclusive shared L3 caches implemented on ISA that requires
>hardware-enforced consistency between I and D caches.
>
>>I thought Intel used write-through to keep levels of
>>cache synchronized.
>
>Only L1D. L2 is WB. But even with WT things remain rather complex.
>
>>Intuitively keeping track of updates from two cores shouldn't
>>be much harder than with just one core, you just need more bandwidth (but thats inherent to sharing cache).
>>
>
>I have very limited understanding of implementation techniques used for inclusive
>caches. It seems to me that the outer cache would have to keep track for the "inner"

It does but it does not have to worry about which inner cache has the line. It just issues the equivalent of a "BRIL zero lenth" to the upper caches when it needs to BI. The upper caches must then invalidate.