Inclusive L3? Wow

Article: ISSCC 2006: Intel Tulsa
By: Linus Torvalds (, February 21, 2006 10:10 am
Room: Moderated Discussions
Michael S ( on 2/21/06 wrote:
>It should be rather complex to build inclusive cache that
>has to stay in synch with not one, not two, but SIX inner

Why would that be complex? I think the Intel L2 is already
inclusive, and so the L3 can totally ignore the L1 I/D side
entirely. So there are just two inner caches that it needs
to worry about.

And the L3 would have to be inclusive if you want all the
coherency logic to be there, and not have to worry about
snooping the L2. Makes perfect sense to me.

Or am I missing something?

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Intel Tulsa Coverage from ISSCCDavid Kanter2006/02/21 02:45 AM
  Intel Tulsa Coverage from ISSCCAlberto2006/02/21 04:43 AM
    Intel Tulsa Coverage from ISSCCPaul DeMone2006/02/21 06:52 AM
  Inclusive L3? WowMichael S2006/02/21 04:51 AM
    Inclusive L3? WowWouter Tinus2006/02/21 07:06 AM
      Inclusive L3? WowMichael S2006/02/21 08:20 AM
        Inclusive L3? Wowslim2006/02/21 11:40 AM
    It is?anonymous2006/02/21 09:57 AM
    Inclusive L3? WowLinus Torvalds2006/02/21 10:10 AM
      Inclusive L3? WowMichael S2006/02/21 11:03 AM
        Inclusive L3? WowLinus Torvalds2006/02/21 11:52 AM
          Inclusive L3? WowEric Bron2006/02/22 06:39 AM
            Inclusive L3David Kanter2006/02/22 12:16 PM
              Inclusive L3Eric Bron2006/02/22 01:00 PM
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