Article: ISSCC 2006: Intel Tulsa
By: Michael S (already5chosen.delete@this.yahoo.com), February 21, 2006 11:03 am
Room: Moderated Discussions
Linus Torvalds (torvalds@osdl.org) on 2/21/06 wrote:
---------------------------
>Michael S (already5chosen@yahoo.com) on 2/21/06 wrote:
>>
>>It should be rather complex to build inclusive cache that
>>has to stay in synch with not one, not two, but SIX inner
>>caches!
>
>Why would that be complex? I think the Intel L2 is already
>inclusive, and so the L3 can totally ignore the L1 I/D side
>entirely. So there are just two inner caches that it needs
>to worry about.
>
>And the L3 would have to be inclusive if you want all the
>coherency logic to be there, and not have to worry about
>snooping the L2. Makes perfect sense to me.
>
>Or am I missing something?
>
>Linus
Yes, you are missing the fact that L2 is not inclusive.
From the latest IA-32 Intel Architecture Optimization Reference Manual:
"Levels in the cache hierarchy are not inclusive. The fact that a line is in level i does not imply that it is also in level i+1. All caches use a pseudo-LRU (least recently used) replacement algorithm."
ftp://download.intel.com/design/Pentium4/manuals/24896612.pdf.
p. 1.20.
Changing L2 cache policy to inclusive would constitute rather big change in the Netburst microarchitecture hardly justifiable by needs of the single low-volume member of the family, especially taking into account that it is most likely the last member.
---------------------------
>Michael S (already5chosen@yahoo.com) on 2/21/06 wrote:
>>
>>It should be rather complex to build inclusive cache that
>>has to stay in synch with not one, not two, but SIX inner
>>caches!
>
>Why would that be complex? I think the Intel L2 is already
>inclusive, and so the L3 can totally ignore the L1 I/D side
>entirely. So there are just two inner caches that it needs
>to worry about.
>
>And the L3 would have to be inclusive if you want all the
>coherency logic to be there, and not have to worry about
>snooping the L2. Makes perfect sense to me.
>
>Or am I missing something?
>
>Linus
Yes, you are missing the fact that L2 is not inclusive.
From the latest IA-32 Intel Architecture Optimization Reference Manual:
"Levels in the cache hierarchy are not inclusive. The fact that a line is in level i does not imply that it is also in level i+1. All caches use a pseudo-LRU (least recently used) replacement algorithm."
ftp://download.intel.com/design/Pentium4/manuals/24896612.pdf.
p. 1.20.
Changing L2 cache policy to inclusive would constitute rather big change in the Netburst microarchitecture hardly justifiable by needs of the single low-volume member of the family, especially taking into account that it is most likely the last member.
| Topic | Posted By | Date |
|---|---|---|
| Intel Tulsa Coverage from ISSCC | David Kanter | 2006/02/21 02:45 AM |
| Intel Tulsa Coverage from ISSCC | Alberto | 2006/02/21 04:43 AM |
| Intel Tulsa Coverage from ISSCC | Paul DeMone | 2006/02/21 06:52 AM |
| Inclusive L3? Wow | Michael S | 2006/02/21 04:51 AM |
| Inclusive L3? Wow | Wouter Tinus | 2006/02/21 07:06 AM |
| Inclusive L3? Wow | Michael S | 2006/02/21 08:20 AM |
| Inclusive L3? Wow | slim | 2006/02/21 11:40 AM |
| It is? | anonymous | 2006/02/21 09:57 AM |
| Inclusive L3? Wow | Linus Torvalds | 2006/02/21 10:10 AM |
| Inclusive L3? Wow | Michael S | 2006/02/21 11:03 AM |
| Inclusive L3? Wow | Linus Torvalds | 2006/02/21 11:52 AM |
| Inclusive L3? Wow | Eric Bron | 2006/02/22 06:39 AM |
| Inclusive L3 | David Kanter | 2006/02/22 12:16 PM |
| Inclusive L3 | Eric Bron | 2006/02/22 01:00 PM |