Inclusive L3? Wow

Article: ISSCC 2006: Intel Tulsa
By: Linus Torvalds (torvalds.delete@this.osdl.org), February 21, 2006 11:52 am
Room: Moderated Discussions
Michael S (already5chosen@yahoo.com) on 2/21/06 wrote:
>
>Yes, you are missing the fact that L2 is not inclusive.

Are you sure?

Not being strictly inclusive would seem to cause many
nasty issues with the L2 having a different line size
than the L1, and also makes it much harder to snoop.

Especially with the L1 running at very high frequencies,
I'd be surprised if it also participates in the
snoop logic, so I would have assumed inclusion from that
if nothing else.

>From the latest IA-32 Intel Architecture Optimization
>Reference Manual:
> "Levels in the cache hierarchy are not inclusive. The
> fact that a line is in level i does not imply that it
> is also in level i+1. All caches use a pseudo-LRU
> (least recently used) replacement algorithm."

That describes the architectural issues, and in particular,
it says that inclusion is not guaranteed. For example, it
is entirely possible that the L3 in previous Netburst cores
(the "EE" ones) wasn't inclusive, but that they decided
to change that, because they wanted to do coherency on the
L3 level.

>Changing L2 cache policy to inclusive would constitute
>rather big change in the Netburst microarchitecture hardly
>justifiable by needs of the single low-volume member of
>the family, especially taking into account that it is most
>likely the last member.

I agree. I would just have expected the L2 to already
be inclusive, especially considering that the L1's are
fairly small, run at a high frequency, and have a different
line length. All of those say "probably inclusive" to me.

The fact that the CPUID information shouldn't be taken
to mean that the caches are inclusive doesn't mean that
they cannot be inclusive. I think the wording is
meant to say that it's not an architected feature.

But hey, you may well be right. I'm just surprised, and
I'd prefer to see a more explicit "the L2 on the P4 is not
inclusive" mention.

Linus
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Intel Tulsa Coverage from ISSCCDavid Kanter2006/02/21 02:45 AM
  Intel Tulsa Coverage from ISSCCAlberto2006/02/21 04:43 AM
    Intel Tulsa Coverage from ISSCCPaul DeMone2006/02/21 06:52 AM
  Inclusive L3? WowMichael S2006/02/21 04:51 AM
    Inclusive L3? WowWouter Tinus2006/02/21 07:06 AM
      Inclusive L3? WowMichael S2006/02/21 08:20 AM
        Inclusive L3? Wowslim2006/02/21 11:40 AM
    It is?anonymous2006/02/21 09:57 AM
    Inclusive L3? WowLinus Torvalds2006/02/21 10:10 AM
      Inclusive L3? WowMichael S2006/02/21 11:03 AM
        Inclusive L3? WowLinus Torvalds2006/02/21 11:52 AM
          Inclusive L3? WowEric Bron2006/02/22 06:39 AM
            Inclusive L3David Kanter2006/02/22 12:16 PM
              Inclusive L3Eric Bron2006/02/22 01:00 PM
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