Article: Cavium MIPSes Network and Security Processing
By: mas (mas769.delete@this.hotmail.com), June 18, 2006 2:41 pm
Room: Moderated Discussions
mas (mas769@hotmail.com) on 6/18/06 wrote:
>mas (mas769@hotmail.com) on 6/18/06 wrote:
>>Really interesting article. Perhaps their biggest competitor is RMI who just bought
>>Alchemy off AMD. They have an 8-core 32-thread SMT MIPS chip. Interesting to see
>>all these new RISC start-ups working under the radar of the big boys ;-).
>>XLR732 Processor
>>The heart of the XLR732 processor consists of an innovative set of XLR™ cores enabling
>>up to 32 threads or virtual CPUs (vCPUs™) in a single chip. The XLR architecture
>>is built around eight XLR-enhanced MIPS64-compatible cores implementing fine-grained,
>>4-way multithreading combined with multi-level hierarchy of caches, autonomous accelerators,
>>and point-to-point interconnects for data and message transfers.
>>The interconnects’ full-speed operation augment application scalability and closely
>>integrate the high performance main memory controllers, level-2 caches, 10Gbps accelerated
>>security operations, and accelerated networking interfaces to deliver a processing
>>solution running at frequencies of 800MHz – 1.2GHz optimized for maximum throughput and workload efficiency.
>>RMI XLR732 Highlights:
>>* Operating Frequency 800MHz – 1.2GHz
>>* 8 Cores with 32 Threads (vCPUs™)
>>* 2MB of Banked 8-way L2 Caches
>>* Four Autonomous Security Acceleration Engines (SAEs) with 10Gbps capacity
>>* 4 x 36bit (144 bit) DDR I/II at 800MHz
>>* 2 x 10GE/SPI 4.2
>>* 4 x 1GEs
>>* 1605 BGA Package
>some more detail

some history


>>David Kanter (dkanter@realworldtech.com) on 6/12/06 wrote:
>>>Hey Everyone,
>>>In the tradition of trying to actually publish regularly, we now have a new article online.
>>>Cavium Networks was founded by a group of industry veterans, including ex Alpha
>>>designers from DEC, and made its mark producing security coprocessors for the networking
>>>industry. However, Cavium's plan is to expand their presence into general networking,
>>>integrating together MIPS compatible processors and dedicated security functions.
>>>The OCTEON family is a system on a chip that scales from 1 to 16 processors, with
>>>a bevy of coprocessors, integrated memory controller and networking functionality.
>>>This article looks at the architecture and existing applications.
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
New Article Online; Cavium Networks OCTEONDavid Kanter2006/06/12 10:14 PM
  New Article Online; Cavium Networks OCTEONRob Thorpe2006/06/13 02:08 AM
  New Article Online; Cavium Networks OCTEONPiedPiper2006/06/13 08:36 PM
    New Article Online; Cavium Networks OCTEONDavid Kanter2006/06/13 10:54 PM
  New Article Online; Cavium Networks OCTEONmas2006/06/18 12:29 PM
    XLRmas2006/06/18 01:06 PM
      XLRmas2006/06/18 02:41 PM
        RMI: Tall talesChuck2006/06/19 06:45 PM
          Are you sure?David Kanter2006/06/19 08:33 PM
    New Article Online; Cavium Networks OCTEONmas2006/06/18 01:50 PM
    Security processorsDavid Kanter2006/06/18 03:52 PM
      Security processorssubmicron2006/06/18 11:09 PM
        I'm not so sureDavid Kanter2006/06/18 11:36 PM
          Food for thought...Dean Kent2006/06/19 07:35 AM
            Food for thought...theo nordsieck2006/06/19 09:48 AM
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