By: Martin H. Kristiansen (email@example.com), August 14, 2006 12:29 am
Room: Moderated Discussions
After going through the Intel documentation it is clear that they have significantly more events to probe than AMD has with CodeAnalyst.
However, I was unable to find if you could trigger event counters on L1 store misses (either trigger directly or deduce them by inference from other counted events).
I think it is interesting to know just how common these are in order to infer how important the store-reordering of Core 2 is, - and also to infer how much the K8L, which will only have load-reordering, will lag behind.
We've discussed earlier that store misses carry as many data dependencies as loads do. I suspect store misses are significantly less frequent than load misses but have no way to get hard data, - at least from CodeAnalyst.
|VTune Article online||David Kanter||2006/08/13 10:10 PM|
|1 ms ticks at 1 khz, 1 us ticks at 1 Mhz||jl||2006/08/13 10:32 PM|
|Events - store misses||Martin H. Kristiansen||2006/08/14 12:29 AM|
|Events - store misses||David Kanter||2006/08/14 09:30 PM|
|Events - store misses||Martin H. Kristiansen||2006/08/15 01:03 AM|
|Events - store misses||anonymous||2006/08/15 06:33 AM|
|Events - store misses||Andi Kleen||2006/08/15 11:12 AM|
|Events - store misses||anonymous||2006/08/15 06:41 PM|
|memory disambiguation||Michael S||2006/08/15 04:54 PM|