Events - store misses

Article: Performance Analysis Tools: A Look at VTune
By: Andi Kleen (ak-rwt.delete@this.muc.de), August 15, 2006 11:12 am
Room: Moderated Discussions
anonymous (no@spam.com) on 8/15/06 wrote:
---------------------------
>>x86 cannot re-order stores.
>
>That statement is a little too generic/simplistic.
>
>For the actual rules, see section 7.2 of Intel's volume 3A (#253668-020).
>
>In particular, check section 7.2.2 rule 3 (CLFLUSH and MOVNT*), as well as section
>7.2.3 (out-of-order fast strings). Speculative TLB fills that set A/D bits are similar.

If he had said "cannot reorder stores cache coherently" he
might have been right though. AFAIK all of these flush
the caches.

That is why i find them often not very useful. They look
great in microbenchmarks, but if you try to actually use
the result the cache misses kill.

Also all the existing implementations seem to have
very small WC reordering buffers only, so they tend
to not hold up very well under high load.

Ok I guess they work for graphics, but probably not
too much else.

< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
VTune Article onlineDavid Kanter2006/08/13 10:10 PM
  1 ms ticks at 1 khz, 1 us ticks at 1 Mhzjl2006/08/13 10:32 PM
  Events - store missesMartin H. Kristiansen2006/08/14 12:29 AM
    Events - store missesDavid Kanter2006/08/14 09:30 PM
      Events - store missesMartin H. Kristiansen2006/08/15 01:03 AM
      Events - store missesanonymous2006/08/15 06:33 AM
        Events - store missesAndi Kleen2006/08/15 11:12 AM
          Events - store missesanonymous2006/08/15 06:41 PM
      memory disambiguationMichael S2006/08/15 04:54 PM
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