Hot Chips 18: Core 2 tidbits

Article: Niagara II: The Hydra Returns
By: anonymous (no.delete@this.spam.com), September 4, 2006 9:15 pm
Room: Moderated Discussions
>Other high performance MPU related presentations at Hot Chips included one on the
>Blackford chipset, the Tulsa MPU, and the Core microarchitecture. The latter was
>mostly a rehash of IDF news, but did include some new details (but not enough to merit a new article).

The interesting new Core 2 tidbits were (IMO)...

- 36 mm^2 and 19 million transistors per core

- L1d has 8 banks and dual-ported tags
- 8 line fill/write combining buffers
- 4 write back buffers

- MOB = 32x loads plus 20x stores

- 32-entry 4-way PDC

- 16-entry 4-way L0 dTLB for small pages
- 16-entry 4-way L0 dTLB for large pages
- 256-entry 4-way L1 dTLB for small pages
- 32-entry 4-way L1 dTLB for large pages

- mention of IP-based prefetcher
(see Intel #314175 for details)

YMMV. :)
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/04 09:01 PM
  Hot Chips 18: Core 2 tidbitsanonymous2006/09/04 09:15 PM
    Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 11:29 AM
      Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 12:33 PM
        Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 12:48 PM
          Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 03:40 PM
            Hot Chips 18: Core 2 tidbitsanonymous2006/09/06 06:20 AM
  Hot Chips 18: Niagara II Article OnlineGarius Bias2006/09/05 01:35 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/05 12:08 PM
  Hot Chips 18: Niagara II Article OnlineChuck2006/09/06 03:59 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/06 08:50 AM
  Hot Chips 18: Niagara II Article OnlineTom W2006/09/08 09:42 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/08 11:18 AM
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