Hot Chips 18: Core 2 tidbits

Article: Niagara II: The Hydra Returns
By: Andi Kleen (ak-rwt.delete@this.muc.de), September 5, 2006 11:29 am
Room: Moderated Discussions

>
>- 16-entry 4-way L0 dTLB for small pages
>- 16-entry 4-way L0 dTLB for large pages
>- 256-entry 4-way L1 dTLB for small pages
>- 32-entry 4-way L1 dTLB for large pages

You would need a presentation for that. This
information is all in CPUID (in the AMD 0x8... space,
but Intel x86-64 implements those too)
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/04 09:01 PM
  Hot Chips 18: Core 2 tidbitsanonymous2006/09/04 09:15 PM
    Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 11:29 AM
      Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 12:33 PM
        Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 12:48 PM
          Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 03:40 PM
            Hot Chips 18: Core 2 tidbitsanonymous2006/09/06 06:20 AM
  Hot Chips 18: Niagara II Article OnlineGarius Bias2006/09/05 01:35 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/05 12:08 PM
  Hot Chips 18: Niagara II Article OnlineChuck2006/09/06 03:59 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/06 08:50 AM
  Hot Chips 18: Niagara II Article OnlineTom W2006/09/08 09:42 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/08 11:18 AM
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