Article: Niagara II: The Hydra Returns
By: anonymous (no.delete@this.spam.com), September 5, 2006 1:33 pm
Room: Moderated Discussions
>>- 16-entry 4-way L0 dTLB for small pages
>>- 16-entry 4-way L0 dTLB for large pages
>>- 256-entry 4-way L1 dTLB for small pages
>>- 32-entry 4-way L1 dTLB for large pages
>
>You would need a presentation for that. This
>information is all in CPUID (in the AMD 0x8... space,
>but Intel x86-64 implements those too)
My Core 2 machines report the following:
0x00000002 = 0x05B0B101,0x005657F0,0x00000000,0x2CB43049
0x05 = undocumented
0xB0 = 128-entry 4-way iTLB
0xB1 = undocumented
0x56 = undocumented
0x57 = undocumented
0xF0 = 64-byte prefetch
0x2C = 32K 8-way 64 bytes/line L1d
0xB4 = undocumented
0x30 = 32K 8-way 64 bytes/line L1i
0x49 = 4M 16-way 64 bytes/line L3
Yes, the L2 is reported as an L3 -- weird.
0x80000005 = 0x00000000,0x00000000,0x00000000,0x00000000
0x80000006 = 0x00000000,0x00000000,0x10008040,0x00000000
That is, no AMD-compatible cache/TLB details are
reported, except for that 4M 16-way 64 bytes/line
L2 cache.
So, until Intel decides to document its undocumented
cache/TLB descriptors, the HotChips 18 presentation
is, uhm, useful.
>>- 16-entry 4-way L0 dTLB for large pages
>>- 256-entry 4-way L1 dTLB for small pages
>>- 32-entry 4-way L1 dTLB for large pages
>
>You would need a presentation for that. This
>information is all in CPUID (in the AMD 0x8... space,
>but Intel x86-64 implements those too)
My Core 2 machines report the following:
0x00000002 = 0x05B0B101,0x005657F0,0x00000000,0x2CB43049
0x05 = undocumented
0xB0 = 128-entry 4-way iTLB
0xB1 = undocumented
0x56 = undocumented
0x57 = undocumented
0xF0 = 64-byte prefetch
0x2C = 32K 8-way 64 bytes/line L1d
0xB4 = undocumented
0x30 = 32K 8-way 64 bytes/line L1i
0x49 = 4M 16-way 64 bytes/line L3
Yes, the L2 is reported as an L3 -- weird.
0x80000005 = 0x00000000,0x00000000,0x00000000,0x00000000
0x80000006 = 0x00000000,0x00000000,0x10008040,0x00000000
That is, no AMD-compatible cache/TLB details are
reported, except for that 4M 16-way 64 bytes/line
L2 cache.
So, until Intel decides to document its undocumented
cache/TLB descriptors, the HotChips 18 presentation
is, uhm, useful.
| Topic | Posted By | Date |
|---|---|---|
| Hot Chips 18: Niagara II Article Online | David Kanter | 2006/09/04 10:01 PM |
| Hot Chips 18: Core 2 tidbits | anonymous | 2006/09/04 10:15 PM |
| Hot Chips 18: Core 2 tidbits | Andi Kleen | 2006/09/05 12:29 PM |
| Hot Chips 18: Core 2 tidbits | anonymous | 2006/09/05 01:33 PM |
| Hot Chips 18: Core 2 tidbits | Andi Kleen | 2006/09/05 01:48 PM |
| Hot Chips 18: Core 2 tidbits | anonymous | 2006/09/05 04:40 PM |
| Hot Chips 18: Core 2 tidbits | anonymous | 2006/09/06 07:20 AM |
| Hot Chips 18: Niagara II Article Online | Garius Bias | 2006/09/05 02:35 AM |
| Hot Chips 18: Niagara II Article Online | David Kanter | 2006/09/05 01:08 PM |
| Hot Chips 18: Niagara II Article Online | Chuck | 2006/09/06 04:59 AM |
| Hot Chips 18: Niagara II Article Online | David Kanter | 2006/09/06 09:50 AM |
| Hot Chips 18: Niagara II Article Online | Tom W | 2006/09/08 10:42 AM |
| Hot Chips 18: Niagara II Article Online | David Kanter | 2006/09/08 12:18 PM |