Hot Chips 18: Core 2 tidbits

Article: Niagara II: The Hydra Returns
By: Andi Kleen (ak-rwt.delete@this.muc.de), September 5, 2006 1:48 pm
Room: Moderated Discussions
anonymous (no@spam.com) on 9/5/06 wrote:
---------------------------
>>>- 16-entry 4-way L0 dTLB for small pages
>>>- 16-entry 4-way L0 dTLB for large pages
>>>- 256-entry 4-way L1 dTLB for small pages
>>>- 32-entry 4-way L1 dTLB for large pages
>>
>>You would need a presentation for that. This
>>information is all in CPUID (in the AMD 0x8... space,
>>but Intel x86-64 implements those too)
>
>My Core 2 machines report the following:
>
>0x00000002 = 0x05B0B101,0x005657F0,0x00000000,0x2CB43049

That's the caches only. And the official new Intel way
to report this is with CPUID 4, 2 is obsolete
because it wasn't extensible.

TLBs are in 0x80000005, 0x80000006

-Andi
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/04 10:01 PM
  Hot Chips 18: Core 2 tidbitsanonymous2006/09/04 10:15 PM
    Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 12:29 PM
      Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 01:33 PM
        Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 01:48 PM
          Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 04:40 PM
            Hot Chips 18: Core 2 tidbitsanonymous2006/09/06 07:20 AM
  Hot Chips 18: Niagara II Article OnlineGarius Bias2006/09/05 02:35 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/05 01:08 PM
  Hot Chips 18: Niagara II Article OnlineChuck2006/09/06 04:59 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/06 09:50 AM
  Hot Chips 18: Niagara II Article OnlineTom W2006/09/08 10:42 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/08 12:18 PM
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