>>>>- 16-entry 4-way L0 dTLB for small pages
>>>>- 16-entry 4-way L0 dTLB for large pages
>>>>- 256-entry 4-way L1 dTLB for small pages
>>>>- 32-entry 4-way L1 dTLB for large pages
>>>
>>>You would need a presentation for that. This
>>>information is all in CPUID (in the AMD 0x8... space,
>>>but Intel x86-64 implements those too)
>>
>>My Core 2 machines report the following:
>>
>>0x00000002 = 0x05B0B101,0x005657F0,0x00000000,0x2CB43049
>
>That's the caches only. And the official new Intel way
>to report this is with CPUID 4, 2 is obsolete
>because it wasn't extensible.

CPUID 0x00000004 is intended to report L1d and L2 details.
Which my Core 2 machines do, as expected. (Except for the
minor weirdness of reporting the L2 twice, for ECX=1 and
for ECX=2.) However, CPUID 0x00000004 is not intended to
report TLB details, and my Core 2 machines don't seem to
be using it for that, e.g. with ECX>2.

So no, unless Intel introduced yet another method, CPUID
0x00000002 is what advertises the TLBs.

>TLBs are in 0x80000005, 0x80000006

What part of...

| 0x80000005 = 0x00000000,0x00000000,0x00000000,0x00000000
| 0x80000006 = 0x00000000,0x00000000,0x10008040,0x00000000
|
| That is, no AMD-compatible cache/TLB details are
| reported, except for that 4M 16-way 64 bytes/line
| L2 cache.

...in my message did you not understand? ;-)