Hot Chips 18: Niagara II Article Online

Article: Niagara II: The Hydra Returns
By: David Kanter (dkanter.delete@this.realworldtech.com), September 6, 2006 9:50 am
Room: Moderated Discussions
>Did Grohoski disclose why they chose one FPU per core rather >than say one per 4-core block?

I didn't think to ask. I would guess that there are several reasons:

1. The FPU also handles complex integer instructions, which may be common enough that sharing is a bad idea performance wise.
2. Perhaps they are going after the HPC market, or some subset thereof?
3. Most importantly, the FPU controls the SPU/crypto unit. They decided they wanted to have wire speed crypto (20Gbit/s) which dictated the number of SPUs. The Modular Arithmetic Unit in the SPU shares the FPU multiplier. Hence, to achieve the same performance, each core would have to include a dedicated multiplier for the MAU, which might be worse in terms of area.
4. More complicated design as you mention.

I think the 3rd reason is the most compelling.

DK
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Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/04 10:01 PM
  Hot Chips 18: Core 2 tidbitsanonymous2006/09/04 10:15 PM
    Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 12:29 PM
      Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 01:33 PM
        Hot Chips 18: Core 2 tidbitsAndi Kleen2006/09/05 01:48 PM
          Hot Chips 18: Core 2 tidbitsanonymous2006/09/05 04:40 PM
            Hot Chips 18: Core 2 tidbitsanonymous2006/09/06 07:20 AM
  Hot Chips 18: Niagara II Article OnlineGarius Bias2006/09/05 02:35 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/05 01:08 PM
  Hot Chips 18: Niagara II Article OnlineChuck2006/09/06 04:59 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/06 09:50 AM
  Hot Chips 18: Niagara II Article OnlineTom W2006/09/08 10:42 AM
    Hot Chips 18: Niagara II Article OnlineDavid Kanter2006/09/08 12:18 PM
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