>Did Grohoski disclose why they chose one FPU per core rather >than say one per 4-core block?

I didn't think to ask. I would guess that there are several reasons:

1. The FPU also handles complex integer instructions, which may be common enough that sharing is a bad idea performance wise.
2. Perhaps they are going after the HPC market, or some subset thereof?
3. Most importantly, the FPU controls the SPU/crypto unit. They decided they wanted to have wire speed crypto (20Gbit/s) which dictated the number of SPUs. The Modular Arithmetic Unit in the SPU shares the FPU multiplier. Hence, to achieve the same performance, each core would have to include a dedicated multiplier for the MAU, which might be worse in terms of area.
4. More complicated design as you mention.

I think the 3rd reason is the most compelling.

DK