Niels Jørgen Kruse (nospam@ab-katrinedal.dk) on 10/17/06 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 10/16/06 wrote:
>---------------------------
>>As I hinted at this weekend, I have just finished up an article on the POWER6:
>>
>>http://www.realworldtech.com/page.cfm?ArticleID=RWT101606194731
>>
>>Just as a caveat, IBM has been releasing information in a very controlled, deliberate
>>and painfully slow manner. The presentation at MPF was largely about the system,
>>not the MPU. Any information about the microarchitecture was largely inferred and implied in their presentation.

>A few comments: The new direct routing scheme would seem to >leave one interMCM
>link unused on every MCM (2 on each CPU chip = 8 total, but >only 7 other MCMs to connect to).

Good point.

>Do you have independent confirmation of the L3 cache size? >The slide that has the
>information seems to show 2 cache chips per CPU chip, where >POWER5 only had one.
>The text says "32MB Non-sectored L3 Cache per chip", which >could be read as either per cache chip or as per CPU chip.

Yup. I spent some time talking with Brad in the afternoon.

DK