Wilco (Wilco.Dijkstra@ntlworld.com) on 11/6/06 wrote:
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>>Which architectures have such cases and don't support unaligned loads?
>
>ARM (till v6), SH2-A and MIPS16 support multiple loads but not unaligned loads.
>Sparc has lbb (but it needs to be 8-byte aligned). 68000 needed 16-bit alignment, 68020 added unaligned.

I'm looking at MIPS16e manual and I can't see any load multiple.

>>With MIPS' solution, the microarchitecture doesn't have to handle such cases, because
>>the two different accesses come from two different instructions and thus, it's consequences
>>can be visible independently.
>
>Yes, it is making the independent effects explicit. But it also forces all future
>implementations to treat them as independent instructions which means more and slower code.

Agreed. I think they should have defined it so that one of the instructions in an unaligned access pair is a ~NOP if the address is aligned. That would have been slick.
The way it is, you just access the word twice over.