Rob Thorpe (rthorpe@realworldtech.com) on 11/14/06 wrote:
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>Wilco (Wilco.Dijkstra@ntlworld.com) on 11/13/06 wrote:
>---------------------------

>>>Branch delay slots, and other pipeline artifacts are much worse.
>>
>>For hardware, definitely! The only exception I know is "Microprocessor without
>>Interlocking Pipe Stages" which was quickly changed to "Microprocessor with Interlocking Pipe Stages" :-)
>
>An interlock is when a microprocessors control logic introduces a bubble into it's
>pipeline to cope with some fixed hazard. This has little to do with branch delay
>slots, which rather fix the existance of bubbles at points in code (and sometimes
>try to reuse them). The existence of branch delay slots did not cause interlocks
>in later designs AFAIK, they just made later control logic more complicated.

I was referring to other pipeline artifacts. One of the worst things you can do is expose the pipeline, like many VLIWs do and the original MIPS design did. They chose not to allow reading of the register that was being loaded between the load and the time it was written, so newer implementations continued to work after interlocks were added. Similarly Itanium demands sequential execution semantics (ie. it disallows swap using 2 moves).

Wilco