foobar (asdf@asdf.com) on 10/17/06 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 10/17/06 wrote:
>---------------------------
>>>Very nice article David but I have a problem with this >statement:
>>>
>>>"The current z9 processor uses the POWER5 as an I/O >processor, and it is expected
>>>that the POWER6 will act as an assist processor for >mainframes."
>>>
>>>Care to elaborate?
>>
>>I can't elaborate too much because I'm not an expert on the subject. However,
>>several folks have indicated to me that existing POWER chips are used as IO assist
>>processors for mainframes and do some other functions.
>>
>>Perhaps Robert Wessel, Dean or someone else who is an actual mainframe specialist can comment?
>>
>>DK
>
>I'm not an expert either, and it's my job :)
>
>The zseries processors are unique. There aren't any POWER5 processors in a z9.
>The differences between CP, SAP, IFL, zAAP, zIIP, etc is simply the code that runs
>on them. They are all z9 "bluefire" processors.
>
>However, the newer channels are SOCs built on PPC 440s. But I wouldn't equate PPC 440 and Power5.
>
>Lots of z9 details will be published soon:
>
>http://www.research.ibm.com/journal/rdpip.html


In addition to the I/O card controllers, there are a bunch of PPC cores scattered around a z9. They're called FSP ("Flexible Support Processors"). There are a pair of Ethernet LANs internal to a z9, and most of the FSPs connect to both. For example, there's a FSP in each power supply, a pair on each processor book, one in each Support Element.

Like foobar, I'm not aware of any of these actually being Power5s.

I do believe that Power5s are used in one or more of IBM's storage controllers.