By: MS (ms.delete@this.lostcircuits.com), December 12, 2006 8:55 am
Room: Moderated Discussions
Del (_@_.com) on 12/12/06 wrote:
---------------------------
>Thanks for great work David! The article is unusually well written, and the animations
>is a great way of illustrating the different architectures. This is a topic where
>even otherwise knowlegdable people often seem totally ignorant, so I believe it is really needed.
>
>What I do miss, and believe really should be covered, is the current multi-core
>architectures from Intel and AMD. Core 2 with it's shared cache for instance. Even
>though you did mention crossbar, I still believe the X2 also should be mentioned in particular.
>
>Another issue is of course comparing to clusters with distibuted memory, and their
>ethernet based communication, but I understand if that broadens the scope too much.
>
>Regards,
>Brask
>
I agree wtih Brask, nice work!
Likewise I think that the confusion about the MOESI protocol used by AMD vs. the real life implementation, that is, the data still need to be written back to main memory would be worth pointing out - same for the shared L3 on the Core2. I know it is difficult to draw a line :)
Regards
Michael
---------------------------
>Thanks for great work David! The article is unusually well written, and the animations
>is a great way of illustrating the different architectures. This is a topic where
>even otherwise knowlegdable people often seem totally ignorant, so I believe it is really needed.
>
>What I do miss, and believe really should be covered, is the current multi-core
>architectures from Intel and AMD. Core 2 with it's shared cache for instance. Even
>though you did mention crossbar, I still believe the X2 also should be mentioned in particular.
>
>Another issue is of course comparing to clusters with distibuted memory, and their
>ethernet based communication, but I understand if that broadens the scope too much.
>
>Regards,
>Brask
>
I agree wtih Brask, nice work!
Likewise I think that the confusion about the MOESI protocol used by AMD vs. the real life implementation, that is, the data still need to be written back to main memory would be worth pointing out - same for the shared L3 on the Core2. I know it is difficult to draw a line :)
Regards
Michael
Topic | Posted By | Date |
---|---|---|
Multiprocessor Article online | David Kanter | 2006/12/11 06:22 PM |
Multiprocessor Article online | Del | 2006/12/12 07:26 AM |
Multiprocessor Article online | MS | 2006/12/12 08:55 AM |