ISSCC 2007 Coverage Online

Article: ISSCC 2007: A Brief Survey
By: Anonymous1 (anon.delete@this.anon.anon), March 26, 2007 11:01 am
Room: Moderated Discussions
David W. Hess (dwhess@banishedsouls.org) on 3/26/07 wrote:
---------------------------
>Anonymous1 (anon@anon.anon) on 3/26/07 wrote:
>---------------------------
>>Thanks for the article. Is PA Semi able to vary the voltage in different domains
>>on the same chip independently? How is this different from Intel's Foxton? From
>>what I understand, Foxton will require no software interaction, whereas PA Semi's chip does. Is this correct?
>
>Intel varies the voltage and clock speed based on instantaneous (8 microseconds)
>power dissipation which varies depending on the current work load to remain within a specific thermal envelope:
>
>http://www.intel.com/technology/magazine/computing/foxton-technology-0905.htm
>http://www.edn.com/article/CA501674.html?partner=enews&industryid=22113
>>
>
>So if you are not making use of the floating point units the voltage and frequency
>are increased up to the thermal limit.
>
>PA Semi is using separate clock domains and power planes for different units to
>minimize the power dissipation which seems like what Intel calls demand-based switching.
>Here each core has an independent voltage and frequency under software control
>much like a low power laptop processor. I understand AMD's upcoming processor does something similar.
>

Thanks (and thanks to David as well). My understanding is that Barcelona is a little different. I believe it is supposed to dynamically and independently adjust frequencies for each core, with no software intervention. I recall reading that there are two voltage planes: one for the cores and L2, and one for the memory controllers and L3 cache. I don't know if it has the ability to dynamically adjust the voltage for these planes.

This brings up a question I raised before, but received no reponse to. If a chip is capable of dynamically adjusting the frequency for different parts, doesn't this change the way these chips will be labeled?

For example, say that within a given TDP, an Itanium chip is typically capable at running at a frequency of up to X for integer code, but Y for floating point. What is the frequency for this processor?

There could be a similar problem for Barcelona. Is it conceivable that within a given TDP, the maximum frequency for single-threaded code is higher than the maximum frequency for code that loads all four cores? If so, how would the CPU be labeled for sales?
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
ISSCC 2007 Coverage OnlineDavid Kanter2007/03/25 11:39 PM
  ISSCC 2007 Coverage OnlineAnonymous12007/03/26 08:16 AM
    ISSCC 2007 Coverage OnlineDavid Kanter2007/03/26 10:28 AM
    ISSCC 2007 Coverage OnlineDavid W. Hess2007/03/26 10:37 AM
      ISSCC 2007 Coverage OnlineAnonymous12007/03/26 11:01 AM
        ISSCC 2007 Coverage OnlineDavid Kanter2007/03/26 11:26 AM
          Looks like Penryn will get single-threaded frequency boostAnonymous12007/03/28 11:03 AM
            Looks like Penryn will get single-threaded frequency boostIntelUser20002007/03/28 10:47 PM
      ISSCC 2007 Coverage OnlineJosé Javier Zarate2007/03/27 04:33 AM
      ISSCC 2007 Coverage Onlineanon2007/03/27 08:57 AM
        ISSCC 2007 Coverage OnlineDavid W. Hess2007/03/27 10:08 AM
          ISSCC 2007 Coverage Onlinesavantu2007/03/27 02:37 PM
            ISSCC 2007 Coverage OnlineDavid Kanter2007/03/27 02:42 PM
        ISSCC 2007 Coverage OnlineDavid Kanter2007/03/27 11:30 AM
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