ISSCC Coverage Continues: Intel's Terascale chip

Article: ISSCC 2007: Intel's Teraflops Design
By: David Kanter (dkanter.delete@this.realworldtech.com), April 2, 2007 11:40 pm
Room: Moderated Discussions
I just wrapped up my first in-depth coverage of a topic for ISSCC 2007. This article focuses on Intel's Terascale research chip. As most folks know, it is an 80 tile design that implements networking on-chip and managed to achieve 1TFLOP/s performance.

http://www.realworldtech.com/page.cfm?ArticleID=RWT040307000414

By and large, the details that were previously emphasized were relatively unimportant. The most interesting details in the Terascale project are the overall architecture, the on-chip network routers, mesochronous interface and clock distribution.

This article focuses on the technical innovations that were shown off at ISSCC.

Enjoy,

David
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TopicPosted ByDate
ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/02 11:40 PM
  Who is right?no one2007/04/03 03:17 AM
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  ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 06:27 AM
    ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 09:26 AM
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    ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 12:24 PM
      ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 12:38 PM
        ISSCC Coverage Continues: Intel's Terascale chipMarcin Niewiadomski2007/04/06 02:14 AM
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                  Plesiosynchronous interfacesDavid Kanter2007/04/10 08:22 AM
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