Who is right?

Article: ISSCC 2007: Intel's Teraflops Design
By: no one (hdfjs.delete@this.fdhs.com), April 3, 2007 3:17 am
Room: Moderated Discussions
"The fifth port is used for connecting to stacked memory, which Intel tells us we'll be hearing about in another quarter or so. For heat reasons the stacked memory will actually be mounted below the teraflop processor die"

http://www.anandtech.com/showdoc.aspx?i=2925&p=4
< Previous Post in ThreadNext Post in Thread >
TopicPosted ByDate
ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/02 11:40 PM
  Who is right?no one2007/04/03 03:17 AM
    Who is right?David Kanter2007/04/03 09:25 AM
  ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 06:27 AM
    ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 09:26 AM
  ISSCC Coverage Continues: Intel's Terascale chipflamingEndian2007/04/03 11:48 AM
    ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 12:24 PM
      ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 12:38 PM
        ISSCC Coverage Continues: Intel's Terascale chipMarcin Niewiadomski2007/04/06 02:14 AM
          CMP Design spaceDavid Kanter2007/04/07 10:55 PM
            CMP Design spaceMarcin Niewiadomski2007/04/09 09:18 PM
              CMP Design spaceDavid Kanter2007/04/09 10:15 PM
                CMP Design spaceAnonymous12007/04/10 07:53 AM
                  Plesiosynchronous interfacesDavid Kanter2007/04/10 08:22 AM
Reply to this Topic
Name:
Email:
Topic:
Body: No Text
How do you spell green?