Who is right?

Article: ISSCC 2007: Intel's Teraflops Design
By: David Kanter (dkanter.delete@this.realworldtech.com), April 3, 2007 9:25 am
Room: Moderated Discussions
no one (hdfjs@fdhs.com) on 4/3/07 wrote:
>"The fifth port is used for connecting to stacked memory, which Intel tells us we'll
>be hearing about in another quarter or so. For heat reasons the stacked memory will
>actually be mounted below the teraflop processor die"

Well, forget about who's right and who isn't. Think about what makes sense. The router has five interfaces, the diagram I included clearly shows that, and one of them isn't mesochronous.

Any external communication needs to go through the router, because otherwise, there would be no way to correct any skew between two adjacent cores. You could end up with totally garbled data, as the signals fire off at the wrong time. That's precisely the point of the mesochronous interfaces - they remove the skew before data goes to each PE. So clearly, the PEs must be able to talk to the routers.

The device presented at ISSCC was not used with SRAM - in the future it will be. That's also what Intel's PR slides indicate, as seen on AT. That's also what Matt and Jerry (the two project managers) indicated.

Just look at diagram 4, I took that directly out of Intel's slides, which are refereed at ISSCC.


It clearly shows one of five inputs coming from the PE, while the other four come from the network. Nothing from SRAM.

Moreover, you'd want the connection to SRAM to be separate - right now, if you used the router and crossbar to talk to SRAM, you'd have contention with the network traffic. You'd need at least 3 virtual lanes in that case, and the crossbar design would change.

Everything I've seen indicates that the router cannot talk to an external SRAM as currently embodied. I think if you look at the diagrams, and think about the architectural implications both ways, you should be able to convince yourself of that.

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TopicPosted ByDate
ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/02 11:40 PM
  Who is right?no one2007/04/03 03:17 AM
    Who is right?David Kanter2007/04/03 09:25 AM
  ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 06:27 AM
    ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 09:26 AM
  ISSCC Coverage Continues: Intel's Terascale chipflamingEndian2007/04/03 11:48 AM
    ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 12:24 PM
      ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 12:38 PM
        ISSCC Coverage Continues: Intel's Terascale chipMarcin Niewiadomski2007/04/06 02:14 AM
          CMP Design spaceDavid Kanter2007/04/07 10:55 PM
            CMP Design spaceMarcin Niewiadomski2007/04/09 09:18 PM
              CMP Design spaceDavid Kanter2007/04/09 10:15 PM
                CMP Design spaceAnonymous12007/04/10 07:53 AM
                  Plesiosynchronous interfacesDavid Kanter2007/04/10 08:22 AM
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