CMP Design space

Article: ISSCC 2007: Intel's Teraflops Design
By: Anonymous1 (anon.delete@this.anon.anon), April 10, 2007 7:53 am
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 4/9/07 wrote:
---------------------------
>If you have a part of the chip running at N GHz and another part at 2N GHz, it's
>not hard to get them to be synchronous. You'd just want to make sure you transfer
>data into the slower part of the chip (N GHz) at only even clock cycles on the fast part. For example:
>
>Fast Region Slow Region
>0 x x
>1 x
>2 x x
>3 x
>4 x x
>
>etc. etc.
>
>So you can send data between the two regions only on even numbered clock cycles.
>That's a pretty easy problem to solve.
>
>With mesochronous circuits, you have to worry about running at different phases,
>which could result in garbage passing between the two clock regions.
>
>DK

Does anyone currently use plesiochronous interfaces? I'm new to this too, so please speak slowly. :-)
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TopicPosted ByDate
ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/02 11:40 PM
  Who is right?no one2007/04/03 03:17 AM
    Who is right?David Kanter2007/04/03 09:25 AM
  ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 06:27 AM
    ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 09:26 AM
  ISSCC Coverage Continues: Intel's Terascale chipflamingEndian2007/04/03 11:48 AM
    ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 12:24 PM
      ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 12:38 PM
        ISSCC Coverage Continues: Intel's Terascale chipMarcin Niewiadomski2007/04/06 02:14 AM
          CMP Design spaceDavid Kanter2007/04/07 10:55 PM
            CMP Design spaceMarcin Niewiadomski2007/04/09 09:18 PM
              CMP Design spaceDavid Kanter2007/04/09 10:15 PM
                CMP Design spaceAnonymous12007/04/10 07:53 AM
                  Plesiosynchronous interfacesDavid Kanter2007/04/10 08:22 AM
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