Plesiosynchronous interfaces

Article: ISSCC 2007: Intel's Teraflops Design
By: David Kanter (dkanter.delete@this.realworldtech.com), April 10, 2007 8:22 am
Room: Moderated Discussions
Anonymous1 (anon@anon.anon) on 4/10/07 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 4/9/07 wrote:
>---------------------------
>>If you have a part of the chip running at N GHz and another part at 2N GHz, it's
>>not hard to get them to be synchronous. You'd just want to make sure you transfer
>>data into the slower part of the chip (N GHz) at only even clock cycles on the fast part. For example:
>>
>>Fast Region Slow Region
>>0 x x
>>1 x
>>2 x x
>>3 x
>>4 x x
>>
>>etc. etc.
>>
>>So you can send data between the two regions only on even numbered clock cycles.
>>That's a pretty easy problem to solve.
>>
>>With mesochronous circuits, you have to worry about running at different phases,
>>which could result in garbage passing between the two clock regions.
>>
>>DK
>
>Does anyone currently use plesiochronous interfaces? I'm >new to this too, so please speak slowly. :-)

I honestly don't know. Part of it stems from the fact that when Intel uses the term mesochronous, it doesn't appear to mean what other people assume it to mean (necessarily).

It seems like it shouldn't be that hard once you've done mesochronous interfaces though. You'd just need to include a large enough buffer in the interface to account for the worse case (or reasonable worst case) timing differences.

Of course, that buffer could get rather large depending on the frequency differential. Suppose the core on one side was in a sleep state, and the other one was active - you'd probably need a way to wake one core up if the buffer gets too full.

I think the way it's done right now is that the cores can sleep independently of the routers on Polaris (in fact, I think the routers have to always stay on).

David
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  ISSCC Coverage Continues: Intel's Terascale chipflamingEndian2007/04/03 11:48 AM
    ISSCC Coverage Continues: Intel's Terascale chipAnonymous12007/04/03 12:24 PM
      ISSCC Coverage Continues: Intel's Terascale chipDavid Kanter2007/04/03 12:38 PM
        ISSCC Coverage Continues: Intel's Terascale chipMarcin Niewiadomski2007/04/06 02:14 AM
          CMP Design spaceDavid Kanter2007/04/07 10:55 PM
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              CMP Design spaceDavid Kanter2007/04/09 10:15 PM
                CMP Design spaceAnonymous12007/04/10 07:53 AM
                  Plesiosynchronous interfacesDavid Kanter2007/04/10 08:22 AM
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