David Kanter (dkanter@realworldtech.com) on 5/6/07 wrote:
---------------------------
>I'd like to thank Euronymous, our newest contributor, who has just posted an article to RWT from MICRO-39.
>
>This report details one of the most important future technologies for semiconductors:
>three dimensional integration. Academic and industrial researchers at Intel and
>IBM have made it clear that 3D integration is the future for semiconductor manufacturing.
>This report explains the major motivations and challenges for 3D integration, how
>this technique works, and the preliminary results that 3D integration can offer for modern microprocessors.
>
>The article can be found at:
>http://realworldtech.com/page.cfm?ArticleID=RWT050207213241
>
>Thanks to Euronymous for providing an excellent, well-thought and informative article
>and I hope everyone enjoys examining a new dimension in semiconductor advances.


With the top-down front-to-back stacked approach, how thick are the upper layers of the stack? I got the impression that these layers are only a few microns thick.

I assume that the back-side vias are made with an extended time implantation procedure, so that you have an n or p well that's substantially deeper than the surrounding transistor structures? Or do they use something more exotic and actually etch a hole and fill it with metal or poly?

Does this start with an ultra thin wafer, or is the top layer somehow cut off after processing?

And how to you reliably handle these (presumably) ultra thin slices?