3D Integration article by new author

Article: 3D Integration: A Revolution in Design
By: slacker (sla.delete@this.c.ker), May 7, 2007 12:40 am
Room: Moderated Discussions
rwessrl (robertwessel@yahoo.com) on 5/7/07 wrote:
>With the top-down front-to-back stacked approach, how thick are the upper layers
>of the stack? I got the impression that these layers are only a few microns thick.

The upper layers are the thickness of the bulk substrate: 300-500 microns (assuming that they are not thinned)

>I assume that the back-side vias are made with an extended time implantation procedure,
>so that you have an n or p well that's substantially deeper than the surrounding
>transistor structures? Or do they use something more exotic and actually etch a hole and fill it with metal or poly?

Actually etch a hole

>Does this start with an ultra thin wafer, or is the top layer somehow cut off after processing?

Wafers are thinned (ground).

>And how to you reliably handle these (presumably) ultra thin slices?

Carefully (mechanical rigidity is a problem).
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3D Integration article by new authorDavid Kanter2007/05/06 06:50 PM
  3D Integration article by new authorrwessrl2007/05/07 12:10 AM
    3D Integration article by new authorslacker2007/05/07 12:40 AM
      3D Integration article by new authorrwessel2007/05/07 12:57 AM
        3D Integration article by new authoryoyo2007/05/07 04:47 AM
  3D Integration article by new authorWierdo2007/05/08 04:57 AM
  3D Integration article by new authorMarcin Niewiadomski2007/05/10 11:14 AM
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