Barcelona optimization guide

By: Vincent Diepeveen (diep.delete@this.xs4all.nl), May 13, 2007 4:20 am
Room: Moderated Discussions
mas (mas769@hotmail.com) on 5/10/07 wrote:
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>http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/40546.pdf

Extremely disappointing at first look. Hopefully a lot of optimizations and tweaks have been done that haven't been described.

It mentions for example latency of multiplication instruction is 5 cycles (!!). Even an instruction like PMULUDQ is 5 cycles whereas i don't see why this can't get done faster.

Integer multiply 64 x 64 bits unsigned == 128 bits also seemingly has a latency of 5 cycles i read at appendix A page 219.

Now i am not so good in counting and speaking for myself here, as i'm not very good in math, so i might have missed it from a previous generation K8, but i tend to remember that it was 4 cycles there, from an email i had.

I was under the probably wrong misconception that it would be able to execute 4 instructions a cycle at integer area.

When i read manual correct i deduce it's executing 3 instructions maximum a cycle.

So Intel has bigger surplus potential of 33% for good programmers, did i read that correct, or am i wrong there and is core2 not having 4 integer units either?

In the optimization manual it prefers to replace short loops of 4x4 already by hand written out code for those 16 cases.

Why can't the processor perfectly predict such loops just like intel seemingly is doing?

It is 2007 now, no longer 1997.

Seems their aim is to serve floating point.

If a problem in its fundament is integer oriented and if you are not capable of rewriting an algorithm to integers, then you need to rethink your solution. Floating point is completely overrated IMHO.

SSEx is not paying enough attention to allow to vectorize integer codes. Putting all cards at floating point AMD obviously tries to conquer the highend market.

It is interesting therefore that AMD already includes popcount into its processor.

Vincent
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