# Barcelona optimization guide

By: Vincent Diepeveen (diep.delete@this.xs4all.nl), May 16, 2007 1:36 am
Dresdenboy (M.Waldhauer@gmx.de) on 5/14/07 wrote:
---------------------------
>Vincent Diepeveen (diep@xs4all.nl) on 5/13/07 wrote:
>---------------------------
>>EduardoS (no@spam.com) on 5/13/07 wrote:
>>---------------------------
>>>The latency is 4 cycles for the lower 64 bits, 5 for the upper, comparing that upper to other processors:
>>>K-8: 5 cycles
>>>C2D: 7 cycles
>>>P4E: 11 cycles
>>>Multiply is a complex instruction, 5 cycles is ok.
>>
>>So if your car can drive at most at 100 KM/h,
>>then it is an ok driving speed considering
>>T-ford getting a speed at most of 40 KM/h ??
>
>But throughput is still 1/cycle for 64 bit muls and 0.5/cycle for 128 bit muls.
>Problem is only, that the result isn't available that quickly, but OOO execution
>will manage to hide that to some extent.

Let's distinguish the questions to the specific instructions:

unsigned integer 64 bits multiply x 64 bits delivering a 128 bits unsigned integer result.

Throughput of 1 how must i interpret that?

Does it mean that it while those 5 cycles of the multiply get spend, the cpu CAN practically execute 4 x 2 = 8 uops of 64 bits unsigned integer bitfiddling in the other 2 execution units?

So in short the improvement in barcelona over the currently sold K8 is that it no longer blocks other execution units during a part of its execution?

Is it correct that Barcelona improved here over current K8?

secondly there is the different SIMD instructions.
When executing a SIMD instruction, for example the one that multiplies 2 doubles * 2 doubles == 2 doubles (a double being a 64 bits floating point with 52+ bits mantissa), which is so crucial for highend calculations, such as research to find new medicines (eating an impressive 0.5% of system time at big supercomputers).

That multiplication eats 5 cycles, and 2 cycles out of those 5 cycles the cpu totally blocks other instructions getting executed, so here we can execute 3 x 2 = 6 uops to integer instructions while that SIMD multiply occurs.

Do i say formulate it correctly like this?

Thanks,
Vincent

>>
>>>>I was under the probably wrong misconception that it would be able to execute
>4 instructions a cycle at integer area.
>>>>
>>>>When i read manual correct i deduce it's executing 3 instructions maximum a cycle.
>>>>
>>>>So Intel has bigger surplus potential of 33% for good programmers, did i read that
>>>>correct, or am i wrong there and is core2 not having 4 integer units either?
>>>
>>>Core 2 have 4 decoders (up to 5 instructions per clock with macro-fusion) but only
>>>3 integer units and can retire only 4 uOPs per cycle, Barcelona isn't too far behind, if any.
>>
>>If core2 can retire 4 uops per cycle and barcelona can retire 3 uops a cycle i
>>understand, then core2 can blow that barcelona core completely away. That's 33% faster speed.
>
>As already said, µOps/MacroOps are different. If an x86 instruction contains complex
>memory operand addresses then C2D has to create at least 2 µops, while already K8
>created only 1 MacroOp then. So 3 MacroOps/cycle mean up to 6 µOps/cycle, but without any explicitly fused ops.
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