Barcelona optimization guide

By: Michael S (already5chosen.delete@this.yahoo.com), May 17, 2007 4:26 am
Room: Moderated Discussions
anonymous (no@spam.com) on 5/16/07 wrote:
---------------------------
>>I have yet to find any code with > 2 uops/cycle, so Intel's 4th issue/execute/retire
>>slot really doesn't help all that much. Nobody consistently has IPC=3...
>
>I can sustain IPC=4, though only for brief periods of time.
>And with little use, at least from a software perspective.

I think if you want to realize Merom's potential for two packed SSE operations per clock on DGEMM-like kernels then you pretty much have to write code with IPC > 3 uoup/cycle although probably less than 3.5 uoup/cycle.

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