Barcelona Article Online

Article: Inside Barcelona: AMD's Next Generation
By: anonymous (no.delete@this.spam.com), May 16, 2007 7:52 pm
Room: Moderated Discussions
>>40-entry IFFRF? Sure?
>>
>>Someone from AMD stated 60-entry a while ago, but I
>>would have to dig up the URL (on another machine).
>
>60 entries is clearly wrong - the IFFRF size is the sum of 16 x86-visible speculative
>registers, 16 x86-visible committed registers and 8 microcode-only registers = 40 total registers.
>
>It's possible an additional 20 microcode scratch registers could have been added,
>but this is highly unlikely, since this would be wasteful - the current microcode never needs more than 8 scratch regs.

Here is what my records say:

Mitch Alsup @ comp.arch @ 2006/10/24 12:10:50 -0700
wrote:
The K8 integer core has 16 (GPR) + 36 (window) + 8 (microcode) = 60 registers of 70-bits each.
The K8 Floating point core has 8 (x87) + 32 (SSE) + 72 (window) + 8 (microcode) = 120 (remapped) registers of 90-bits each.
The execution of either microcode or macrocode (x86) does not reference anything but the architectural {GPR, x87, SSE) registers (other than the microcode temp regs.)
The basic unit of integer execution is a load-op-store which hardly looks RISC-like in any real sense of the word.
Load-op-stores are tripple scheduled out of the reservation stations (which is not RISC-like either).
The basic unit of work is 70-odd bits wide (which is hardly RISC-like).
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