Great read. Thanks.

Just a few things:

"...16 XMM registers, which actually occupy 2 slots, since they are 128 bits wide."

This is true for the K8, but not for Barcelona.
From the AMD 10h optimization guide:

"A floating-point XMM register is viewed as one 128-bit register internal to the processor.
Current generation processors cannot write a 64-bit half of a 128-bit XMM register without having a merge dependency on the other 64-bit half."

Also, the K8/Barcelona diagrams would seem to suggest that data is stored from LSU1 and loaded to LSU2, but that's not the case as you yourself have written in the article.
Stores are written (after retirement) from LSU2 exclusively. While loads can be initialized from either LSU1 or LSU2, the actual data is passed directly to the IFFRF (and can be cough by a reservation station or ALU on the way there).

From the same diagram: FPMISC should present its data directly to LSU1, instead of going through a reservation station.
And a typo: 44 Entry Integer Future File – should be 40.