Barcelona Article Online

Article: Inside Barcelona: AMD's Next Generation
By: Dean M (dean.m8.delete@this.gmail.com), May 16, 2007 2:10 pm
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 5/16/07 wrote:
---------------------------
>So my diagrams did take a little liberty. I am extremely constrained by the available
>space that I have. My diagrams must be 750p wide, no more, and the Barcelona one
>was already pushing up against the limits to the point where at the end I had to
>clip out 16 pixels from the L2 and L3 cache basically to get it to fit.
>
>The diagram is meant to indicate that the 64 bit addresses go from LSU1-->cache
>tags. 128 bit data comes back from the cache, and 64 bit data goes in. Unfortunately,
>I didn't have enough room to stick in address, read data and write data lines, without
>things getting ugly. I'd call it an unfortunate artistic compromise.
>

Guess I forgot about diagram size constraints. I bet it would have been a nightmare drawing the whole forwarding network.

>Isn't FPMISC also used for integer<-->FP conversions? I was trying to make the
>point that the FPMISC pipeline is used to get data between the two functional unit clusters, rather than FPSTORE.
>

FPMISC is used for fp<->int conversions, but now that you mention it, how does Barcelona handles data movement between fp and int registers?
AFAIK, on the K8 there was no fast way of doing it - AMD recommended avoiding it as much as possible. Now, on Barcelona register to register MOVD is a fastpath instruction so AMD recommends using it for fp to int register movs, but still recommends avoiding int to fp register movs (a store and load from memory is preferable).

So did the data have to pass through the LSU on the K8, but can now move directly from the fp to the int register file? (But not the other way around?)
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      macro-op vs. micro-opMichael S2007/05/22 05:26 AM
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