IntelUser2000 (Intel_user2000@yahoo.ca) on 5/16/07 wrote:
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>David Kanter (dkanter@realworldtech.com) on 5/16/07 wrote:

>I always thought Conroe had fully pipelined FPU from >looking at your article, but
>its not true.
>It still has the same FPU latency for FPMUL as its P6 >derivatives.

Fully pipelined has nothing to do with the latency, but with how often you can issue the instructions. For instance, if you have a unit which executes an instruction with latency 10000000000 cycles, but can issue an instruction every cycle...it's fully pipelined. It's not very useful, but it's fully pipelined.

What does Intel's latest optimization manual say?

>BTW, why would they take the legacy FPU to 128-bit anyway?? >I think they are still
>64-bits, exactly similar to Yonah. Barcelona did not change >its FPU, only SSE units
>were enhanced, same is very likely true with Conroe.

My understanding was that the FPU and SSE units in Conroe use the same circuitry, but with slightly different front-ends. That could be wrong, but I seem to recall that standing out from our discussion.

DK