microops vs macroops on page 4

Article: Inside Barcelona: AMD's Next Generation
By: Peter Lund (firefly.delete@this.vax64.dk), May 17, 2007 12:04 pm
Room: Moderated Discussions
From page 4 of your article:

"Like the Pentium Pro, the K7/8 has an internal instruction set which is fairly RISC-like, composed of micro-ops."

A microop on an AMD microarchitecture is not something that "can include one load, a computation and a store" -- it's the macroop that can do that.

The decoders generate macroops, often with a straight-forward one-to-one relationship to the macroinstructions, so that a single macroop contains for example a source register, an operation, a data size, and a complicated address specification that is used for both loading and storing an "accummulator-like" operand from/to memory.

Such macroops can be broken down further into microops later on in the pipeline, where one microop is a single load or store or operation (or address generation?).

-Peter
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            Stop comparing apples to orangesEduardoS2007/05/22 02:30 PM
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          macro-op vs. micro-opdess2007/05/24 09:38 AM
      macro-op vs. micro-opMichael S2007/05/22 05:26 AM
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