Peter Lund (firefly@vax64.dk) on 5/17/07 wrote:
---------------------------
>From page 4 of your article:
>
>"Like the Pentium Pro, the K7/8 has an internal instruction >set which is fairly RISC-like, composed of micro-ops."
>
>A microop on an AMD microarchitecture is not something that >"can include one load,
>a computation and a store" -- it's the macroop that can do >that.

>The decoders generate macroops, often with a >straight-forward one-to-one relationship
>to the macroinstructions, so that a single macroop contains >for example a source
>register, an operation, a data size, and a complicated >address specification that
>is used for both loading and storing an "accummulator-like" >operand from/to memory.

>Such macroops can be broken down further into microops >later on in the pipeline,
>where one microop is a single load or store or operation >(or address generation?).

Is there an AMD document somewhere that makes all this clear?

Because from talking to architects, they don't really care quite so much about the names, rather what they mean. I had an email exchange with someone from AMD and we got a little confused and we settled on 'internal op' as the most precise way of describing this.

Just as a note, I really dislike the fact that AMD cannot stick with specific terminology.

http://studies.ac.upc.edu/ETSETB/SEGPAR/microprocessors/amdk7%20(mpr).pdf

Once upon a time AMD apparently had x86-->macro op-->risc op. Hard to keep those straight, especially when AMD keeps changing the definitions. I tried to be fairly clear, and perhaps I'll chat with some folks to straighten all this out.

DK