dess (dess@nospam.com) on 5/21/07 wrote:
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>The article speak about (as well as the figures indicate) >micro-ops at some places,
>where - IMHO - there should be macro-op, instead. F.ex.:
>"The pack buffer, which is part of the decoding phase, is >responsible for sending
>groups of exactly 3 micro-ops to the re-order buffer (ROB)."
>An exerpt from the Software Optimization Guide for AMD 10h >Processors:
>"Early decoding produces three macro-ops per cycle from >either path. The outputs
>of both decoders are multiplexed together and passed to the >next stage in the pipeline, the instruction control unit."
>(AFAIK a macro-op can contain several micro-ops.)

In talking with architects, some use the terminology micro-op to refer to what AMD used to call RISCops (Rops), but are most accurately described as internal operations. Some of their documentation refers to macro-ops as the internal operations. I don't really think it matters. I choose the term that makes it easiest for the folks at AMD to edit/revise/comment on my article and questions.

However, Intel is a different story. First of all, the term is uop, not micro-op, which refers to the internal operations. In Intel terminology a macro-op is an x86 instruction. So macro-op fusion is the fusing of two x86 instruction (CMP+JMP).

>Now I'm confused whether this happened at some places for >the Core 2 as well, or
>those are really 4 micro-ops, in which case the Barcelona >is the wider one.

Decoding always maps the contents of the Icache (x86 instructions) to the internal operations and operands of the processor in question.

AMD has 3 decoders, Intel has 4 decoders. AMD can 3 operations/cycle, Intel can rename 4. Counting execution units is a little tricky since AMD likes to count their separate AGUs as functional units, while Intel considers them part of the memory pipelines. Intel can retire 4 operations, AMD can retire 3.

At the end of the day, the Core2 is theoretically wider. However, it's unclear to what extent this will be true in practice.

DK